1. Technical Field
The disclosure relates to a semiconductor integrated circuit and, more particularly, to a data output clock signal generating apparatus in a semiconductor integrated circuit that generates a stable data output clock signal.
2. Related Art
Conventional semiconductor integrated circuits, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), include data output buffers that output data read from a memory cell array to the outside of the semiconductor integrated circuit. As a result, data, which is synchronized with a data output clock signal, is output to an input/output pad via the data output buffer. The data output clock signal can be generated by delaying an external clock signal by a predetermined amount of time.
The external clock signal and the data output clock signal can share the same swing level, or range. That is, the voltage level of the external clock signal and the data output clock signal can have the same voltage range. Typical the range is from the voltage level of an external driving power supply, which is an operational upper-limit potential, to a voltage level of a ground terminal, which is an operational lower-limit potential.
In recent years, high speed operation has become a must for semiconductor integrated circuits, because most electronic equipment operates at a high speed. However, if the external driving power supply voltage is low, the external clock signal and the data output clock signal also operate in a low voltage range. This can negatively effect the data access time (hereinafter, referred to as ‘tAC’) for data that is output in synchronization with a data output clock having a low operational voltage level. Meanwhile, if the operational voltage is increased by a predetermined voltage to improve the tAC, it becomes difficult to satisfy a data hold time (hereinafter, referred to as ‘tOH’), in which the data needs to be maintained for a predetermined amount of time to stably output the data.